1. Field of the Invention
The present invention relates to a method for forming high resistance resistor. More particularly, the present invention relates to a method for forming a high resistance resistor with integrated high voltage device process.
2. Description of the Prior Art
Isolation is provided in a semiconductor between transistors on a semiconductor chip to prevent unwanted electrical connections there between. On the development of ultra-large-scale-integrated (ULSI), layout rule will shrink and the application of product is going to invent on multi-chip of integrated function.
In conventional methods, a substrate 10 comprise a implemented N-well 12, and a field oxide area 20 is formed on the substrate 10, wherein the N-well is a high resistance area of high voltage device such as shown in FIG. 1. A mixed-mode process can provide a process flow with embedded capacitor in logic circuit. The additional capacitor can be used for RC analog circuit or other special applications. A first electrode 30 of capacitor is formed on the field oxide area 20. An interpoly dielectric layer 40 such as oxide-nitride-oxide (ONO) layer is formed on the first electrode 30. A second electrode 50 of capacitor is formed on the oxide-nitride-oxide layer 40. The first electrode 30 and second electrode 50 are comprised polysilicon layer. An interlevel dielectric layer 70 is formed over the substrate 10 and capacitor. Then etch interlevel dielectric layer 70 to form a plurality contact hole. A conductive material is deposited to form contacts. Such as a contact 65 connect to high concentration area of N-well 60, a contact 32 connect to first electrode 30 and contact 52 connect to second electrode 50 of capacitor.
However, in the conventional process to form a high resistance resistor with an integrated high voltage device process, the high resistance area of N-well is pre-formed in the substrate. Then to be continued process to a formed capacitor has several thermal treatments then will induce a variation of devices. They will cause different bias voltage.
It is therefore an objective of the invention to provide a method of manufacturing a high voltage device. The capacitor and high resistance resistor are formed by the same fabricating step.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for forming a high resistance resistor with an integrated high voltage device process.
In this invention, a process in the formation of a high resistance resistor with an integrated high voltage device process is desired. A substrate comprised explanation a field oxide area. An un-doped polysilicon layer is deposited on the field oxide area. An interpoly dielectric layer such as oxide-nitride-oxide (ONO) layer is formed on the un-doped polysilicon layer. Then etch oxide-nitride-oxide layer and processing ion implant process by BF2 implant to the un-doped polysilicon layer. Adjusting dosage of BF2 controls the resistance of resistor. An interlevel dielectric layer such as silicon oxide is formed on the substrate and the resistor. The silicon oxide layer is etched to form contact holes. An ion implant process is performed to reduce resistance between contact and resistor by BF2 radical. The thermal rapid processing (RTP) increased ion diffusion of ion implant and a metal is deposited to formed contact.
In this invention, the high voltage device combined with mixed mode processes by using un-doped polysilicon layer instead of the conventional polysilicon layer. First the source region and drain region is formed, then the high resistance area with ion implant. In this high resistance area: first, etch oxide-nitride-oxide layer, second, ion implant process by using BF2 radical to the un-doped polysilicon layer to form resistor. Adjusting dosage of BF2 controls the resistance. Next performing contact etched, the high dosage of BF2 implant to high resistance area to reduce resistance between contact and resistor.